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Shure DP11EQE Dynamics Processor Specification: GENERAL: Frequency Response: 20 to 20k Hz +/- 1.0 dB re 1 kHz Dynamic Range: 104 dB minimum, A-weighted, 20 Hz to 20 kHz Sampling Rate: 48 kHz Digital-to-Analog, Analog-to-Digital Conversion: 20 bit resolution Voltage Gain: 1 dB +/- 1dB (power off) 12 dB +/- 2 dB (input 10 dBV, output +4 dBu) 12 dB +/- 2 dB (input +4 dBu, output 10 dBv) 0 dB +/- 2 dB (equal input and output sensitivities) Impedance: Input: 47 kilohms +/- 20% actual Output: 120 ohms +/- 20% actual Input Clipping Level +18 dBu minimum (at +4 dBu setting) +6 dBV minimum (at 10 dBV setting) Output Clipping Level +18 dBu minimum (at +4 dBu setting) +6 dBV minimum (at 10 dBV setting) Total Harmonic Distortion LED Signal Indicators Signal: 40 dB Clip: 6 dB down from input clipping Propagation Delay from Input to Ouput 0.8 ms (all filters flat, no dynamics processing, 0 ms delay), up to 2.1 ms (all processing enabled) Polarity Input to output: inverting optional (default: non-inverting) XLR: pin 2 positive with respect to pin 3 1/4-inch TRS: tip positive with respect to ring Operating Voltage DP11EQ: 120 Vac, 50/60 Hz, 50 mA max DP11EQE: 230 Vac, 50/60 Hz, 25 mA max DP11EQJ: 100 Vac, 50/60 Hz, 50 mA max Temperature Range Operating: 0 degrees to 60 degrees C (32 degrees to 140 degrees F) Fuse DP11EQ: 120 Vac. Fuse: 100 mA, 250V time delay DP11EQE: 230 Vac. Fuse: 50 mA, 250 V time delay DP11EQJ: 100 Vac. Fuse: 100 mA, 250 V time delay Dimensions 219 mm x 137 mm x 44 mm (8-5/8 in x 5-3/8 in x 1-3/4 in) Weight: 930 g (2.05 lbs) DYNAMICS PROCESSOR Gate and Expander: Threshold: 72 to 1 dB, 0.5 dB resolution Attack: 1.0 to 200 ms Decay: 0.05 to 1 second Gate Hold Time: 0 to 0.5 seconds AGC Leveler Threshold: 72 to 1 dB, 0.5 dB resolution Attack: 0.2 to 3 seconds Decay: 0.5 to 5 seconds Hinge: Threshold to 1 dB, 0.5 dB resolution Compressor and Limiter Threshold: 72 to 1 dB, 0.5 dB resolution Attack: 1.0 to 200 ms Decay: 0.05 to 1 second Knee: Hard or Soft selectable No Overshoot Peak Limiter Propagation delay: 1 ms Threshold: 72 to 1 dB, 0.5 dB resolution Attack: 0 msDecay: 100 ms PARAMETRIC EQUALIZER Parametric Filter Frequency Bands Up to 9 bands, variable frequency, variable Q Boost/Cut Range +6 dB to 18 dB per band Q Range 1/40-octave to 2 octave High and Low Shelf/Cut Filters Shelf, +6 to 18 dB per filter Cut, 12 dB per octave nominal DELAY Up to 1.3 seconds, 21 microsecond resolution
The Multicom Pro-XL MDX4600 gives you 4 channels of first-class dynamic control in a single rack space. With a multitude of new features like the advanced program-adaptive expander gate, extensive metering plus a variety of configuration options, the Multicom Pro-XL puts a lot of dynamic processing power in your rack.
Features Switchable IKA (Interactive Knee Adaptation) program-adaptive compression circuitry combines the advantages of hard-knee and soft-knee characteristics IRC (Interactive Ratio Control) expander/gate circuitry for virtually inaudible noise suppression Switchable dynamic enhancer for brilliant, lively audio even with heavy compression IGC (Interactive Gain Control) peak limiting circuitry combines clipper and program limiter for reliable and inaudible protection against signal peaks Switchable low contour filter prevents "pumping" due to low-frequency dominated compression Stereo couple function selectable for channels 1/2 and 3/4 Ultra low-noise 4580 operational amplifiers and state-of-the-art THAT¬ VCA's Separate 8-segment LED meters for input/output levels and gain reduction Selectable operating level (+4 dBu/-10 dBV) High-quality detented ALPS¬ potentiometers and illuminated switches Servo-balanced inputs and outputs with ? in. TRS and gold-plated XLR connectors Manufactured under ISO9000 certified management system
The latest addition to the 10 Series product line, the dbx® 1074 QuadGate™, is the perfect companion to the 1066 and 1046. The 1074 offers 4 channels of gating with threshold, depth and release controls on each channel. The 1074, like the rest of the products in dbx 10 Series, is based on the legendary dbx V2 VCA and offers XLR inputs and outputs, and 1/4” side-chain input. In addition to an external key input per channel, the 1074 also has an internal filter that can be independently activated and controlled on a channel-per-channel basis. This filter allows the 1074 to not only clean up tracks, but gives you frequency selective control on each gate, to open exactly when you want it to. These features combined, make the 1074 an absolute must for those who require quad gating on applications including: Gating dry and percussive sounds such as snare drum and kick drum,gating sounds that have longer decay times such as cymbals and Pianos, gating hum or buzz from live instruments or recorded tracks or eliminating Headphone leakage into microphones. Gating instrument microphones to eliminate amplifier bleed. From the company that has been redefining the standard of signal processing for more than 30 years, dbx® Professional Products comes a bulletproof product that caters to the scrutinizing needs of those who require the precision noise gating capabilities. Once again, the engineering staff at dbx® Professional Products have taken technology that has been over three decades in the making and have created a product that is flexible, versatile and rock solid in construction design. The 1074ʼs independent channel design with key filtering capabilities make it the perfect tool for countless applications.
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Hybrid Memory Cube (HMC) is a high-performance computer random-access memory (RAM) interface for through-silicon via (TSV)-based stacked DRAM memory. HMC competes with the incompatible rival interface High Bandwidth Memory (HBM).
Hybrid Memory Cube was co-developed by Samsung Electronics and Micron Technology in 2011,[1] and announced by Micron in September 2011.[2] It promised a 15 times speed improvement over DDR3.[3] The Hybrid Memory Cube Consortium (HMCC) is backed by several major technology companies including Samsung, Micron Technology, Open-Silicon, ARM, HP (since withdrawn), Microsoft (since withdrawn), Altera (acquired by Intel in late 2015), and Xilinx.[4][5] Micron, while continuing to support HMCC, is discontinuing the HMC product [6] in 2018 when it failed to achieve market adoption.
HMC combines through-silicon vias (TSV) and microbumps to connect multiple (currently 4 to 8) dies of memory cell arrays on top of each other.[7] The memory controller is integrated as a separate die.[2]
HMC uses standard DRAM cells but it has more data banks than classic DRAM memory of the same size. The HMC interface is incompatible with current DDRn (DDR2 or DDR3) and competing High Bandwidth Memory implementations.[8]
HMC technology won the Best New Technology award from The Linley Group (publisher of Microprocessor Report magazine) in 2011.[9][10]
The first public specification, HMC 1.0, was published in April 2013.[11] According to it, the HMC uses 16-lane or 8-lane (half size) full-duplex differential serial links, with each lane having 10, 12.5 or 15 Gbit/s SerDes.[12] Each HMC package is named a cube, and they can be chained in a network of up to 8 cubes with cube-to-cube links and some cubes using their links as pass-through links.[13] A typical cube package with 4 links has 896 BGA pins and a size of 31×31×3.8 millimeters.[14]
The typical raw bandwidth of a single 16-lane link with 10 Gbit/s signalling implies a total bandwidth of all 16 lanes of 40 GB/s (20 GB/s transmit and 20 GB/s receive); cubes with 4 and 8 links are planned, though the HMC 1.0 spec limits link speed to 10 Gbit/s in the 8-link case. Therefore, a 4-link cube can reach 240 GB/s memory bandwidth (120 GB/s each direction using 15 Gbit/s SerDes), while an 8-link cube can reach 320 GB/s bandwidth (160 GB/s each direction using 10 Gbit/s SerDes).[15] Effective memory bandwidth utilization varies from 33% to 50% for smallest packets of 32 bytes; and from 45% to 85% for 128 byte packets.[7]
As reported at the HotChips 23 conference in 2011, the first generation of HMC demonstration cubes with four 50 nm DRAM memory dies and one 90 nm logic die with total capacity of 512 MB and size 27×27 mm had power consumption of 11 W and was powered with 1.2 V.[7]
Engineering samples of second generation HMC memory chips were shipped in September 2013 by Micron.[3] Samples of 2 GB HMC (stack of 4 memory dies, each of 4 Gbit) are packed in a 31×31 mm package and have 4 HMC links. Other samples from 2013 have only two HMC links and a smaller package: 16×19.5 mm.[16]
The second version of the HMC specification was published on 18 November 2014 by HMCC.[17] HMC2 offers a variety of SerDes rates ranging from 12.5 Gbit/s to 30 Gbit/s, yielding an aggregate link bandwidth of 480 GB/s (240 GB/s each direction), though promising only a total DRAM bandwidth of 320 GB/sec.[18] A package may have either 2 or 4 links (down from the 4 or 8 in HMC1), and a quarter-width option is added using 4 lanes.
The first processor to use HMCs was the Fujitsu SPARC64 XIfx,[19] which is used in the Fujitsu PRIMEHPC FX100 supercomputer introduced in 2015.
JEDEC's Wide I/O and Wide I/O 2 are seen as the mobile computing counterparts to the desktop/server-oriented HMC in that both involve 3D die stacks.[20]
In August 2018, Micron announced a move away from HMC to pursue competing high-performance memory technologies such as GDDR6 and HBM.[21]
